1. Field of the Invention
The present invention relates to devices for independently driving several LEDs (Light-Emitting Diodes), such as segments of a digital LED display.
2. Discussion of the Related Art
FIG. 1A shows a conventional driver for the segments of a LED display. Such a driver is commonly used in digital clock displays. The LED segments are grouped by pairs and the control of both LEDs of each pair is multiplexed. FIG. 1A shows the driver coupled to one pair of LEDs LD1, LD2. Both LEDs LD1, LD2 are controlled by an output stage 10 comprising a P-MOS transistor MP1 whose source is connected to a high supply terminal Vcc and whose drain is connected to the anodes of both LEDs LD1, LD2. The gate of transistor MP1 is connected to a reference voltage node P through a switch S1 and to terminal Vcc through a switch S2. Switches S1 and S2 are controlled in phase opposition. When one of the LEDs LD1, LD2 is to be turned on, switch S1 is closed and switch S2 is opened, which turns on transistor MP1. Transistor MP1 is turned off when switch S1 is opened and switch S2 is closed. Switch S2 is necessary to discharge the gate capacitance of transistor MP1.
The cathodes of LEDs LD1 and LD2 respectively receive two different phases .phi.1 and .phi.2 of a rectified sinusoidal voltage taken from the mains.
FIG. 1B shows the two phases (.phi.1 and .phi.2 of the sinusoidal voltage. The sinusoidal voltage is referenced to the supply voltage Vcc. Phase .phi.1 corresponds to the negative half periods of the sinusoidal voltage and phase .phi.2 corresponds to the negatively rectified positive half periods of the sinusoidal voltage. LED LD1 can only turn on when phase .phi.1 exceeds its threshold voltage Vt1. Similarly, LED LD2 can only turn on when phase .phi.2 exceeds its threshold voltage Vt2. Thus, there are time intervals at the beginning and at the end of each phase where both LEDs LD1 and LD2 are always off, even though transistor MP1 is on.
The output stages 10 coupled to all the controlled pairs of LEDs are connected to a common reference source 11 with which the output stages 10 form a multiple output current mirror. Reference stage 11 comprises a P-MOS transistor MP2 having its source connected to the supply voltage Vcc and its drain connected to ground GND through a current generator 13. The gate and drain of transistor MP2 are connected together and constitute the node P where the reference voltage for the output stages 10 is taken. The current supplied to each LED LD1, LD2 is equal to the current provided by the current generator 13, multiplied by the size ratio between transistors MP1 and MP2. This size ratio is relatively large, because a LED requires a relatively large current, usually in the range of 6 mA-30 mA.
LED drivers of the type of FIG. 1A, especially in digital display clocks, are often realized in P-MOS technology. P-MOS technology is becoming obsolete and will no longer exist in the coming years. However, some P-MOS technology circuits are still being widely used. Therefore, there is a tendency to adapt the old P-MOS circuits to new technologies. This is not always easy, especially if the new circuits must have the same specifications as the old circuits, in particular the maximum supply voltage of about 15 V.
The LED driver of FIG. 1A cannot be directly realized in CMOS technology, since current CMOS transistors will accept maximum supply voltages of only 5 V or less.
FIG. 2 shows a possible implementation of the circuit of FIG. 1A in bipolar technology. Bipolar transistors accept higher voltages than CMOS transistors. The P-MOS transistors MP1 and MP2 are replaced by PNP transistors QP1 and QP2. To avoid an undesirable influence which would be caused by the base current taken by transistor QP1, transistor QP2 has only its base connected to node P and an additional PNP transistor Q3 has its emitter connected to node P, its collector connected to ground GND and its base connected between transistor QP2 and current generator 13. This reduces the influence of the base current of transistor QP1 by a factor .beta. (the gain of transistor Q3).
A drawback of this circuit is encountered during the time intervals where the phases .phi.1 and .phi.2 have not yet reached the thresholds Vt1 and Vt2 of the LEDs LD1, LD2. In this case, when transistor QP1 is on, the high current that would normally flow through LED LD1 or LD2, flows into transistor Q3 through the emitter-base junction of transistor QP1. The base current of transistor QP1 is then a factor .beta. (gain of transistor QP1) higher than in normal operation, which causes a considerable increase in power consumption.